Workshop on Stochastic Computing for Neuromorphic Architectures (SCONA2020)

13 March 2020, ALPEXPO, Grenoble, France (co-located with DATE 2020)

Workshop on Stochastic COmputing for Neuromorphic Architectures

Artificial Intelligence applications are a major driver in the hardware development of smart systems. An unprecedented number of proposals for better neuromorphic and neuro-inspired hardware architectures have been suggested, ranging from extremely large and high-performance “wafer-scale” circuits to emerging nano-electronic device-based circuits for storing and manipulating information. The proposed workshop looks at neuromorphic hardware from a different perspective: How to provide sufficient AI and ML performance in applications with extremely limited resources like area, power and energy. Among such approaches, stochastic computing promises outstanding area- and power-efficiency because it offers very compact and reliable realizations of the basic arithmetic operations found in a broad range of neuromorphic applications. The workshop SCONA will bring together researchers working on stochastic computing and resource-limited neuromorphic architectures.

Workshop organizers:

John P. Hayes (University of Michigan, Ann Arbor, USA)
Ilia Polian (University of Stuttgart, Germany)
Weikang Qian (Shanghai Jiao Tong University, China)

Preliminary Program

Workshop on Stochastic COmputing for Neuromorphic Architectures
This program is preliminary. The workshop still accepts submissions!

Friday, March 13, 2020, ALPEXPO Grenoble

Stochastic Computing for Signal Processing and Machine Learning
Warren J. Gross, McGill University, Canada

Speaker's Bio

Warren J. Gross received the B.A.Sc. degree in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1996, and the M.A.Sc. and Ph.D. degrees from the University of Toronto, Toronto, ON, Canada, in 1999 and 2003, respectively. He is a Professor and Louis-Ho Faculty Scholar in Technological Innovation in the Department of Electrical and Computer Engineering, McGill University, Montreal, QC, Canada. He currently serves as Chair of the Department. His research interests are in the design and implementation of signal processing systems and custom computer architectures. Dr. Gross served as the Chair for the IEEE Signal Processing Society Technical Committee on Design and Implementation of Signal Processing Systems. He served as the General Co-Chair for the IEEE GlobalSIP 2017 and the IEEE SiPS 2017 and the Technical Program Co-Chair for SiPS 2012. He served as an Associate Editor for the IEEE Transactions on Signal Processing and as a Senior Area Editor. He is a recipient of the William and Rhea Seath Award in Engineering Innovation. He is a Licensed Professional Engineer in the Province of Ontario.

PASCA: PArallel Stochastic Computing based Neural Network Accelerators
Runsheng Wang, Peking University, China

Tsetlin Machine: A New Paradigm for Pervasive AI
Adrian Wheeldon1, Rishad Shafik1, Alex Yakovlev1, Jonathan Edwards1, Ibrahim Haddadi1, Ole-Christoffer Granmo2, 1Newcastle University, UK. 2University of Agder, Norway.

Introduction to Dynamic Stochastic Computing
Siting Liu, Jie Han, University of Alberta, Canada


From Unary to Low-Discrepancy: Deterministic Bit-streams Revolutionize Stochastic Computing
Hassan Najafi, University of Lousiana in Lafayette, USA

Stochastic magnetic devices for cognitive computing
Kaushik Roy, Purdue University, USA

Stochastic learning in CMOS integrated HfO 2 based memristive arrays
F. Zahari1, M. K. Mahadevaiah2, E. Perez2, E. Perez-Bosch Quesada2, H. Kohlstedt1, Ch. Wenger2,3, M. Ziegler4, 1Kiel University, Germany, 2IHP, Germany, 3Brandenburg Medical School Theodor Fontane, Germany, 4TU Ilmenau, Germany

Workshop Wrap-Up

Call for Papers

The workshop invites submissions on, but not limited to, the following topics:

  • Stochastic primitives for neural networks and other neuromorphic architectures
  • Neuromorphic hardware architectures based on stochastic computing
  • Methods for design, synthesis, analysis, and verification of stochastic circuits
  • Stochastic circuits and architectures based on emerging technologies
  • Applications of neuromorphic stochastic architectures and case studies

The workshop will be co-located with the DATE 2020 conference. At least one author of each accepted paper is expected to register using DATE’s regular registration system. DATE workshops have no formal proceedings but SCONA will prepare an informal electronic proceedings distributed to the workshop participants.

Key dates:

Submission Deadline:
Acceptance Notification:
Final version for workshop proceedings:

January 20, 2020
January 30, 2020
February 15, 2020

Author instructions:

Submissions in form of full 6-page papers or 1-2 page extended abstracts (in IEEE double-column format) should be sent to Ilia Polian by email.

Ilia Polian
Prof. Dr. rer. nat. habil.

Ilia Polian

Head of Institute and Chair of Hardware Oriented Computer Science

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